1. Field of the Invention
The present invention relates generally to the field of electronic circuitry, and more particularly to relatively precise calibration of an analog preamplifier.
2. Description of the Related Art
Relatively precise calibration of analog devices can be highly challenging, particularly in advanced applications wherein analog device calibration errors can significantly affect overall performance or, in certain cases, damage the device or fail. For example, magnetic random access memory (MRAM) circuits can require precision calibration of analog circuits contained therein.
Changes in circuit environmental parameters, most notably temperature and supply voltages, have previously been sensed using circuits having digital outputs to either flags warning of system environmental changes and a need to recalibrate, or the digital outputs directly change the state of the calibration registers.
Previous attempts to provide precision analog calibration include, for example, providing a coarse calibration function for offset compensation using a digitally controlled, resistor voltage divider array and a static switchable current source in place of an adjustable current source. Such a device is illustrated in FIG. 1, where FIG. 1 is taken from U.S. Pat. No. 6,262,625 to Pemer et al. assigned to Hewlett Packard Company, the assignee of the present invention. The '625 patent is hereby incorporated by reference, particularly for an extensive description of the components and operation of shown in FIG. 1. The circuit of FIG. 1 performs a basic coarse calibration function in discrete large calibration steps. Coarse calibration circuit 14 performs coarse correction by applying a back gate voltage bias Vcc+ and Vcc− to the isolated wells of the first and second PMOS transistors 18a and 18b. Certain fine calibration adjustments are also provided. FIG. 2, also taken from the '625 patent, illustrates the details of coarse calibration circuit 14, where the coarse calibration circuit 14 includes a pair of programmable voltage dividers 28 and 36 for developing back gate voltages Vcc+ and Vcc−, and each voltage divider 28 and 36 is connected between a source of operating potential, VDD, and a reference potential GND.
Simple coarse/fine correction can be inefficient, ineffective, and time consuming and can be unworkable in certain applications. Generally, these coarse/fine corrections can degrade overall performance, particularly when recalibration is required. Thus solutions have been proposed that include providing for finer calibration step, such as coarse, fine, and extra fine calibration steps. Such a varied calibration step design can more efficiently control the back gate bias of an array of transistors comprising a CMOS differential pair of transistors. Such a design improves offset control by providing for more exact calibration steps, but still only enables discrete digital steps to control the state of the control registers, again not highly efficient.
A further improvement over existing calibration solutions in this environment provides for UP/DOWN control of registers storing the state of the back gate control information. Within narrow control limits, such a design reduces the overall time for calibration and/or recalibration by stepping the state of the calibration control registers one minimum step at a time. In cases where radical changes in calibration state are required, such as outside a desired range, control of the calibration registers can take a significant amount of time. Further, if wide swings occur in short periods of time, the UP/DOWN control method cannot acquire the required state quickly enough. An additional design provides for a diode element across the back gate divider circuits to address the issue of VDD sensitivity. Such a construction places a voltage control element in the back gate bias network. The power source is similar to the static switchable current source provided in the '625 patent. One additional design provides an analog control circuit to adjust an internal node of the CMOS amplifier to control offset changes. Such a circuit can be difficult to implement relative to the back gate bias control circuit.
These prior solutions consider primarily digital control of a set of registers controlling the back gate bias of the CMOS differential pair transistors. These solutions require time performing recalibration and can only control the calibration in discrete steps, which is inefficient and/or imprecise in many instances.
It would be advantageous to provide a digitally controlled calibration circuitry that can quickly and efficiently control states of independent circuits employed in advanced applications, such as MRAM, where the circuitry tends to result in generally improved performance over previous designs.